1. Technical Field
The disclosure is related generally to integrated circuits (IC). More particularly, the disclosure is related to methods for testing ICs in a wafer and testing structures for integrated circuits.
2. Related Art
Conventionally, semiconductor wafers undergo a testing process before the wafers are cut into usable chips. The testing process helps manufacturers determine operational characteristics of the ICs included in the wafer. More specifically, by performing a testing process on the ICs, manufacturers may determine the electrical characteristic or capabilities of the ICs and/or may determine if the circuits of the wafer include any undesirable electrical faults (e.g., shorts), created during the manufacturing process of the wafer.
Typically, the wafers are tested by inserting a test probe directly into an electrically-conductive material formed within the ICs of the wafer. The test probe may provide manufacturers with desirable data relating to the operational characteristics of the ICs included in the wafer. However, by inserting the test probe directly into the material of the ICs, the ICs become damaged, and may subsequently include faults or operational issues as a result of the damage caused by the test probe. In conventional processes, after the probe is inserted into the ICs, the wafer may undergo an additional reflowing process, where additional material is added to fix the damaged portion of the wafer (e.g., tested ICs) and/or the materials included in the ICs of the wafer are manipulated (e.g., heated, compressed) to fix the damaged area. This reflowing process adds an additional step to the manufacturing process of the wafers, which results in an increase in manufacturing time and/or cost. Additionally, the reflowing process performed after the testing of the wafer may not result in completely fixing the damaged wafer, which ultimately results in undesirable performance the ICs formed from the wafers.